This invention relates to a semiconductor device, particularly but not exclusively a vertical bipolar transistor, and to a method of manufacturing such a semiconductor device.
A semiconductor device has previously been proposed, as described in, for example, Washio et al IEEE transactions on Electron Devices Vol. 35, No. 10, October 1988, which comprises a semiconductor body having adjacent one major surface a first device region of one conductivity type having a relatively highly doped subsidiary region spaced from the one major surface by a relatively lowly doped subsidiary region, a second device region of the opposite conductivity type formed within the relatively lowly doped subsidiary region of the first device region adjacent the one major surface and having an intrinsic subsidiary region forming a first pn junction with the relatively lowly doped subsidiary region and an extrinsic subsidiary region surrounding the intrinsic subsidiary region and forming a second pn junction with the relatively lowly doped subsidiary region, the first and second pn junctions being reverse-biassed in at least one mode of operation of the device, and a third device region of the one conductivity type formed within the intrinsic subsidiary region adjacent the one major surface.
The device described in the aforementioned paper is a vertical bipolar transistor, the word vertical being understood herein to refer to a device in which the main current flow is between opposed major surfaces of the semiconductor body. The relatively lowly doped subsidiary region which forms part of the collector region is defined as a mesa structure having a side wall bounded by an insulating region and the extrinsic subsidiary region of the second device, that is the base, region is formed by diffusion of impurities out of a doped connection layer provided on the insulating region into the mesa structure via its side wall with the doped connection layer enabling electrical contact to be made to the base region. This paper is concerned with the fact that the extrinsic base region can extend quite close to the relatively highly doped subsidiary region of the collector region, resulting in a high collector-base junction capacitance which will cause a reduction in breakdown voltage and detrimentally affect the high frequency performance. In order to enable the extrinsic base subsidiary region to be well spaced from the relatively high doped collector region so as to avoid excessively high collector-base junction capacitances which would otherwise cause a reduction in the collector-base breakdown voltage, this paper proposes a relatively complicated two-step oxidation process which enables the insulating region to be relatively thick and which reduces the size of the window via which impurities from the doped connection layer diffuse into the mesa structure at its side wall.
In addition to the problem discussed above, the Early effect is an important consideration when designing such bipolar transistors. This effect, which causes an increase in current amplification .beta.o(hfe) with collector-emitter voltage V.sub.CE and thus a lack of saturation in the common-emitter output characteristics of the transistor, results from the modulation of the base width W.sub.B with the collector-emitter voltage V.sub.CE. The voltage to which the output characteristic curves of collector current I.sub.c against V.sub.CE for different base currents I.sub.B can be extrapolated at V.sub.CE =0 is referred to as the Early voltage V.sub.eaf. It is an aim of the designers of, in particular, analog bipolar transistors suitable for use in integrated circuits to increase, that is make more negative, the Early voltage V.sub.eaf because this implies a smaller change in .beta..sub.o with V.sub.CE and thus more linear characteristics for the transistor.